DESCRIPTION |
Current |
Future |
LAYOUT |
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| Minimum Line/Spacing, Internal Layers | 0.004 | 0.003 |
| Minimum Line/Spacing, External Layers | 0.004 | 0.003 |
| Minimum Hole Land Diameter over hole | 0.010 | <.010 |
| Minimum Conductor to Edge | 0.004 | 0.003 |
| Soldermask Clearance | 0.003 | 0.002 |
BOARD CONSTRUCTION |
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| Minimum Dielectric thickness | 0.003 | 0.002 |
| Maximum PCB thickness | 0.187 | 0.250 |
| Layer to Layer Registration tolerance | 0.005 | <.005 |
| Minimum Leaded Component Pitch | 10 mils | 10 mils> |
| Through Hole | 0.008 | <.008 |
| Blind (Drilled) | 0.008 | <.008 |
| Blind (Laser) | NO | YES |
| Buried (Drilled) | 0.008 | <.008 |
| Buried (Laser) | NO | YES |
| Maximum Board Size (inches) | 16.25 x 24.00 | 20.00 x 24.00 |
| Layer Build up Combinations | Various & Many | Various & Many |
DRILLED HOLES and VIAS |
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| Minimum Hole Diameter | 0.008 | <.008 |
| Maximum Aspect Ratio-Thickness to Hole Diameter | 10 to 1 | < 10 to 1 |
| Minimum Unplated Hole Size Tolerance | plus/minus .002 | plus/minus .001 |
| Minimum Plated Hole Size Tolerance | plus/minus .002 | plus/minus .002 |
| Minimum Plated Hole Positional Tolerance TPD | plus/minus .001 | plus/minus .0008 |
| Minimum Unplated Hole Positional Tolerance TPD | plus/minus .001 | plus/minus .0008 |
SURFACE FINISHES |
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| HASL | Yes | Yes |
| OSP | No | Yes |
| Electroless Nickel/Gold and thickness | Yes <10 micro | Yes |
| Electrolytic Nickel/Gold and thickness | Yes >30 micro | Yes |
| Others | White Tin | |
| Immersion Silver | ||
BOARD MATERIALS |
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| FR-4 High Temp | Yes | Yes |
| Polyimide | Yes | Yes |
| RF Materials | Rogers & Teflon | Rogers & Teflon |
| BT | No | No |
| BN300 | No | No |
| Others | GML1000 | |
ELECTRICAL DESIGN |
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| Impedance Tolerance (%) | plus/minus 5-10% | plus/minus 0-5% |
ELECTRICAL TEST METHODS |
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| Flying Probe | Flying Probe | |
| Bed of Nails | Bed of Nails | |
| Flying Grid | ||